Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device, which operates at a high speed, performing a clock alignment training operation.
Semiconductor devices are used to store data of a system that they belong to. The semiconductor devices are provided with the data by a data process device of the system, (e.g., a memory control unit) to store data in response to addresses inputted from the data process device. When the data process device requests data stored in the semiconductor devices, the semiconductor devices output data corresponding to addresses inputted from the data process device.
For this, semiconductor devices for operating at high speeds that have recently been developed are designed to input/output two data (e.g., two data bits) between a rising edge and a falling edge of a system clock, which is inputted from an external device, and input/output another two data between the falling edge and the next rising edge of the system clock. That is, the semiconductor device input/outputs four data during a period of the system clock.
However, the system clock has only two states (i.e., logic high and low states). In order to input/output four data during one period of the system clock, the semiconductor device needs a data clock having a frequency higher than that of the system clock. For example, a data clock at double the frequency, compared with the system clock, is used as a reference clock for the input/output of the data.
The semiconductor device receives commands and addresses in response to the system clock, and input/outputs data in response to the data clock by controlling the data clock to have double the frequency than that of the system clock. Therefore, two periods of the data clock are matched with one period of the system clock. The semiconductor device input/outputs data at both rising and falling edges of the data clock. Therefore, four data can be inputted/outputted during one period of the system clock.
Compared with semiconductor devices using one system clock as a reference clock for read/write operations, semiconductor devices in accordance with the embodiment of the present invention use plural clocks having different frequencies than each other for read/write operations. Accordingly, it is necessary to synchronize the plural clocks for semiconductor devices to operate normally. That is, phases of a system clock and a data clock need to be aligned, otherwise the timings for transferring commands/addresses and data are mismatched and the semiconductor devices cannot operate normally. Therefore, at the initial operation of the semiconductor device, training operations, such as interface training, are performed between the semiconductor device and a data process device.
The interface training represents an operation for training the semiconductor device and the data process device prior to their normal operation, in order for commands, addresses, and data to be transferred at the optimum interface. The interface training includes an address training, a clock alignment training (WCK2CK Training), a read training, and a write training. During the clock alignment training, a system clock and a data clock are aligned.
FIG. 1 is a block diagram illustrating a conventional clock alignment training circuit of a semiconductor device.
As described above, a semiconductor device receives commands and addresses from an external controller (i.e., a data process device) on the basis of a system clock HCK, and input/outputs data on the basis of a data clock WCK. Especially at the write operation, the semiconductor device outputs data corresponding to the received commands and addresses to the external controller on the basis of the data clock WCK. If the phase of the system clock HCK is not aligned with that of the data clock WCK, the data may be outputted to the external controller sooner or later than they are requested to be.
To output the data at desired timings, at the initial operation of the semiconductor memory device, a clock alignment training circuit detects a phase difference between the system clock HCK and the data clock WCK received from the controller. The clock alignment training circuit transfers the detected phase difference to the controller to reduce the phase difference. This process of detecting and reducing the phase difference is referred to as the clock alignment training.
Referring to FIG. 1, the clock alignment training circuit includes a clock input block 100, a clock division block 120, a phase detection block 140, and a signal transfer block 160. The clock input block 100 receives the system clock HCK and the data clock WCK. As described above, the system clock HCK is a reference clock for synchronizing the inputs of commands and addresses. The data clock WCK is a reference clock for synchronizing the inputs of data, which has a frequency higher than the system clock HCK.
The clock division block 120 divides the data clock WCK to generate a data division clock DIV_WCK having the same frequency as the system clock HCK. The phase detection block 140 detects the phase difference between the system clock HCK and the data division clock DIV_WCK to generate a detection signal DET_SIG corresponding to the detection result (i.e., the detected phase difference). The signal transfer block 160 outputs the detection signal DET_SIG as a training information signal TRAINING_INFO_SIG to an external controller.
FIG. 2 is a signal timing diagram illustrating an operation of the clock alignment training circuit shown in FIG. 1.
Referring to FIG. 2, the frequency of the data clock WCK, inputted to the clock alignment training circuit, is greater than that of the system clock HCK. The frequency of the data division clock DIV_WCK, divided from the data clock WCK by the clock division block 120, is equal to that of the system clock HCK.
However, edges of the system clock HCK and the data clock WCK (or the data division clock DIV_WCK) are not aligned with each other prior to the clock alignment training operation (e.g., at a point of time marked as {circle around (1)} in FIG. 2). That is, before the clock alignment training operation starts, the phase of the system clock HCK is not synchronized with that of the data clock WCK.
After the clock alignment training operation starts (e.g., at a point of time between time points marked as {circle around (2)} and {circle around (6)}), the phase of the data clock WCK is adjusted, so that the phases of the data clock WCK and the system clock HCK are synchronized with each other.
At this time, the phase of the data clock WCK changes in response to the training information signal TRAINING_INFO_SIG outputted by the signal transfer block 160. Depending on the logic level of the training information signal TRAINING_INFO_SIG (e.g., a logic low level) the external controller, which receives the training information signal TRAINING_INFO_SIG, changes the phase of the data clock WCK to be outputted to the clock alignment training circuit.
As the phase of the data clock WCK becomes synchronized with that of the system clock HCK (at a point of time marked as {circle around (6)}), the training information signal TRAINING_INFO_SIG transitions from a logic low level to a logic high level. In the period (marked as {circle around (7)}) where the training information signal TRAINING_INFO_SIG is maintained in the logic high level, the phase of the data clock WCK no longer changes. That is, depending on the logic high level of the training information signal TRAINING_INFO_SIG, the external controller outputs the data clock WCK having its phase fixed. In conclusion, the clock alignment training circuit continuously compares the phases of the data clock WCK and the system clock HCK, and outputs the comparison result to an external controller, until the phases of the data clock WCK and the system clock HCK are synchronized with each other.
As the clock alignment training circuit is provided to the semiconductor device, it is possible to perform the clock alignment training operation at a power-up time, when the semiconductor device is supplied with a supply voltage at initial operation. However, there is a need to perform the clock alignment training operation at an exit time, when the semiconductor device exits from a specific operation mode.
The semiconductor device has a power down mode for reducing its power consumption, and does not input/output data in that mode. Accordingly, only the system clock HCK is inputted to the semiconductor device in the power down mode (i.e., the data clock WCK is not inputted). However, at the end of the power down mode, the data clock is inputted to the semiconductor device again. Therefore, the phase of the data clock WCK may have changed, so that it is not synchronized with the phase of the system clock HCK. The clock alignment training operation must be performed at the end of operation modes of the semiconductor device, such as the power down mode, in order to synchronize the phases of the data clock WCK and the system clock HCK.
During the entry/exit process of the power down mode, it creates noise, which makes a jitter factor on the data clock WCK. The jitter factor is one of the reasons of a change in the phase of the data clock WCK. However, it rarely occurs, and even if it does, the data clock WCK with the changed phase can be synchronized with the system clock HCK through the clock alignment training operation in a relatively short time.
Turning off component parts of the clock alignment training circuit in the power down mode may affect the whole operation of the semiconductor device. Particularly, as the clock division block 120 is turned off/on in the entry/exit process of the power down mode, the timing of a clock division becomes misaligned. The power down mode may cause the data clock WCK to have its phase inverted. In this case, the clock alignment training circuit would have to change the phase of the data clock WCK by more than a ½ clock period in order to synchronize the phases of the data clock WCK and the system clock HCK. Further, synchronizing the phases of the data clock WCK and the system clock HCK takes a long time, and may delay the whole operation of the semiconductor device. Moreover, the higher the frequency of the system clock HCK and the data clock WCK, the more serious the delay problem becomes.